1. Technical Field
The present invention relates to a buried gate type semiconductor device, a method of fabricating the same, and a module and system having the same, and more particularly, to technology related to improving gate-induced drain leakage (GIDL) and reducing a gate resistance, and thus improving device characteristics and reliability.
2. Related Art
Demand for higher capacity memory such as dynamic random access memories (DRAM) continues to increase while the size available for memory in many devices decreases or remains the same. Therefore, recent endeavors have focused on reducing a cell area by changing a cell layout to integrate more many memory cells on one wafer.
Buried gate structures have been developed as a result of these endeavors. In buried gate structures, a leakage current is increased by GIDL between a conductive material (gate electrode) and an N type junction of an active region or between the conductive material and a storage node contact, and consequently refresh characteristics such as a refresh period (tREF) of the semiconductor device are degraded.
To prevent the leakage current from being increased due to the GIDL, the conductive material (gate electrode) of the buried gate can be over-etched to minimize an overlapping area between the storage node contact and the gate conductive material (gate electrode).
However, while over-etching the conductive material (gate electrode) of the buried gate can reduce leakage current, it also causes the speed and current driving capability of the semiconductor device to be lowered and write-recovery time (TWR) to be degraded due to an increase in resistance of the buried gate.